Due to the technological growth and user demand, data transfers are increasing dramatically in all areas of communications. For example, data streams for digital video, HDTV, and color graphics are requiring higher and higher bandwidth. The sheer volume of available high-quality high-resolution content is one driving force for high-speed interconnects between chips, functional boards, and systems.
These advances have been driven by integrated circuit scaling which has significantly increased the sample rates attainable by processors, data converters, and digital transceivers over the last decade. The desire for both high speed and high resolution in these systems can require chip-to-chip data rates in excess of 100 Gb/s. To support this input bandwidth, compact on-chip receivers are needed which minimize area and power without adding undue complexity to the design. However, current paradigms in chip-to-chip communications tend to push designers to one of two extremes: multiplexing dozens of low-speed data lines to aggregate the desired throughput or serializing the data using synchronized SERDES (SERializer/DESerializer) channels operating at tens of Gb/s.
Though effective, both of these techniques display distinct disadvantages when feeding high-speed mixed-signal blocks. In the first case, implementing dozens of low-speed lines consumes large amounts of chip and PCB real estate in the form of I/O pads, multiplexing circuitry, and board traces. High-speed SERDES systems overcome these issues by reducing I/O pins and board routing by serializing the input data. The implementation of such systems, however, is considerably more complex than the low-speed parallel option. High-speed SERDES receivers must equalize incoming data to account for channel loss, decipher the encoding used to maintain DC balance, and parallelize the result for use on-chip. These steps add significant overhead to any design and increase system complexity dramatically. Ideally, efficient high speed data throughput may be achieved at speeds between these two extremes, reducing the total number of channels as compared with a more parallel approach while avoiding the high channel rates which require equalization, encoding, and other overhead.
From a design perspective, the data of interest may be digital, but often analog topologies are selected to drive these high-speed transmission lines. As an example, the Low Voltage Differential Signaling (LVDS) protocol (IEEE Std 1596.3-1996) is a physical layer standard for digital wireline communications (by way of example, see FIG. 1). This protocol implements a high speed, low power differential architecture to minimize electronic noise and ensure high fidelity data reception. To maintain a performance baseline, the LVDS protocol sets many characteristics of the communications interface including a 1.125 V to 1.275 V output common mode, a 250 mV to 400 mV output data swing, a 100 mV receiver sensitivity, and a 25 mV receiver hysteresis. Additionally, an input common mode voltage range of 0.1 V to 2.3 V is required of the receiver to account for differences in ground potentials between the transmitter and receiver.
Low-voltage differential signaling is a generic interface standard for high-speed data transmission, utilizing high frequency analog circuit techniques to provide multi-gigabit data transfers over wireline interconnects. While the IEEE 1596.3-1996 standard specifies the physical layer as an electronic interface, this standard defines driver and receiver electrical characteristics only. It does not define protocol, interconnect, or connector details as these aspects are application specific.
The LVDS differential driver produces odd-mode transmission: equal and opposite currents flowing in the transmission lines. The current returns within the wire pair, so the current loop area is small, and therefore generates the lowest amount of electro-magnetic interference (EMI). The current source limits any spike current that could occur during transitions. Since there are no spike currents, multi gigabit data rates are possible without a substantial increase in power dissipation. In addition, the constant current driver output can tolerate transmission lines shorted together, or to ground, without creating thermal problems.
The differential receiver is a matched device that detects low amplitude differential signals and then amplifies them into standard logic levels. The signal has a typical driver offset of 1.2 V while the receiver accepts an input range of 0.1 V to 2.3 V. This input range eliminates the issues associated with differing ground potentials and allows for the rejection of common mode noise picked up along the interconnect of up to ±1 V.
In addition, hot swapping of LVDS drivers and receivers is possible because the constant current drive eliminates damage potential. The LVDS interconnect also enables failsafe functionality, which prevents output oscillations when the input pins are floating. For these reason (high speed, low power, noise control, and cost advantages) LVDS is a popular choice in short-range, point-to-point systems for telecommunications, data communications, displays, and application specific data transfer.
However, the LVDS wide input range proves increasingly difficult to accommodate as transistor sizes scale and supply voltages drop below 1.5 V. Current wireline communication systems achieve the necessary input common mode range by resorting to slow, thick-gate transistors capable of handling the large voltage range or by altogether removing the DC variation with AC coupling capacitors. Typical implementation of both these methods provides sub-optimal results by sacrificing speed and size to meet the LVDS specification for input voltage range. For thick-gate transistor implementations, the increased layout size and associated parasitics reduce the maximum speed of the receiver. Alternately, AC coupled implementations typically make use of large, board mounted capacitors for coupling. This methodology consumes vast board area and requires data encoding to maintain DC balance.
As a result, there exists a need in the art for an LVDS type interconnect having on-chip form factor capacitors for AC coupling while enabling reliable transmission of unencoded data during periods of sustained logic output and having tolerance to process, voltage, and temperature (PVT) variations.